(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for preventing the accumulation or agglomeration of silicon-cobalt deposits after a Rapid Thermal Heating process during the creation of salicided surfaces.
(2) Description of the Prior Art
The creation of semiconductor devices frequently uses implantation of impurities into a semiconductor surface, typically the surface of a silicon monocrystalline substrate. The implantation of impurities into the surface of a silicon substrate is aimed at changing the conductive properties of the implanted surface by creating well-known impurity regions that form an integral part of a functional semiconductor device. As examples of such regions of impurity implantations can be cited well regions over which for instance Complementary Metal Oxide Semiconductor (CMOS) gate electrodes are created, Lightly Doped Drain (LDD) regions and source/drain regions that form a functional part of the CMOS devices. In addition to implantation of impurities into the surface of a semiconductor substrate, impurity implantation is used to control a desired level of conductivity in the gate layer of the gate electrode that forms the CMOS device.
After a semiconductor device such as a CMOS device has been created, electrical access to the device must be provided. This electrical contact must, for reasons of device performance, among other requirements be a low-resistivity contact. The process of salicidation is well known in the art, typical salicided layers can be formed comprising titanium silicide (TiSi2), nickel silicided (NiSi), nickel alloy silicide (Ni(metal)Si) and cobalt silicide (CoSix).
The method of self-aligned silicide (salicide) formation, which self-registers with the contacts at the top of the polysilicon gate, the source and the drain, solves the problem of critical dimension tolerance. Salicides have thus become almost universal in high-density CMOS devices even though the gate metal is now frequently replaced by the polysilicon gate. There are, however, problems associated with prior art methods of salicide formation. One main problem is that the salicidation process of converting a refractory metal to its silicide is achieved by the consumption of silicon underlying the metal, and this means the consumption of substrate silicon in the regions of the source and drain. The source/drain junctions, already very shallow in sub-half-micron devices, can become unpredictably extremely thin. A further and very severe problem is that the salicidation reaction can consume substrate silicon unevenly, leading to ragged source/drain junctions and, even worse, the creation of spikes that can penetrate through the junctions near the edges of the source/drain areas.
Another problem that is experienced when forming a CoSix layer of salicided material is that concentrations or agglomerations of CoSix will appear in the surface of the created salicided layer. It has been experimentally determined that the reason for the appearance of CoSix agglomerations is that an insufficient concentration of silicon (Si) is present in the created layer of CoSix. This insufficiency of Si concentration becomes apparent during steps of thermal anneal that are typically performed after the layer of cobalt has been deposited and selectively etched. The invention addresses this issue and provides a method whereby the insufficiency of Si that is characteristic of the created layer of CoSix is removed, thereby removing the occurrence of Coxe2x80x94Si agglomerations.
U.S. Pat. No. 6,242,348 (Kamal et al.) shows a silicide process using an implant.
U.S. Pat. No. 6,207,563 (Wieczorek et al.) shows a two-step anneal in a silicide process.
U.S. Pat. No. 5,904,564 (Park) reveals a CoSix process.
U.S. Pat. No. 5,624,869 (Agnello et al.) and U.S. Pat. No. 5,915,197 (Yamanaka et al.) are related silicide patents.
A principle objective of the invention is to provide a method that prevents agglomeration of Coxe2x80x94Si in created layers of cobalt salicided material.
In accordance with the objectives of the invention a new processing sequence is provided for creating salicided layers of CoSix. A conventional gate electrode is formed up to the point where the process of salicidation has to be performed. At that time a layer of cobalt is deposited over the surface of the gate electrode, a first anneal is applied to the deposited layer of cobalt. The layer of cobalt is then selectively etched to form the contact surfaces of the gate electrode after which, significantly and as a major deviation from previous methods of creating a salicided layer of CoSix, silicon is implanted into the surface of the created layer of CoSix. This silicon implant relieves a silicon deficiency in the first annealed layer of CoSix, this silicon deficiency has experimentally been determined as being the essential cause for the occurrence of Coxe2x80x94Si agglomeration after a second thermal anneal. After the silicon implantation has been completed, a second thermal anneal is applied to the created layer of CoSix. The occurrence of Coxe2x80x94Si agglomeration is in this manner essentially eliminated.